From 2be378903319a00bbf9502cec9ce538119569b98 Mon Sep 17 00:00:00 2001 From: RainBus Date: Fri, 1 Dec 2023 10:26:25 +0800 Subject: [PATCH] vault backup: 2023-12-01 10:26:25 --- Books/HDLBits/Verilog.md | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Books/HDLBits/Verilog.md b/Books/HDLBits/Verilog.md index 3bd6663..3aa5897 100644 --- a/Books/HDLBits/Verilog.md +++ b/Books/HDLBits/Verilog.md @@ -1,3 +1,4 @@ ## Basics ### Wire -Wire is directional. \ No newline at end of file +Wire is directional. We often use `assign lhs = rhs` drive the right signal to left. This assignment is a **continuous**(the change of right will conducted to left immediately when the voltage change), it's not a one-time assignment. +The port(input and output) on a module also have a direction.