From 790358c69abad8ef79aca0941f3319190a18f1f2 Mon Sep 17 00:00:00 2001
From: RainBus <rainandbus@gmail.com>
Date: Fri, 1 Dec 2023 17:53:39 +0800
Subject: [PATCH] vault backup: 2023-12-01 17:53:39

---
 Books/HDLBits/Verilog.md | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/Books/HDLBits/Verilog.md b/Books/HDLBits/Verilog.md
index 3aa5897..f9f608f 100644
--- a/Books/HDLBits/Verilog.md
+++ b/Books/HDLBits/Verilog.md
@@ -1,4 +1,8 @@
-## Basics
-### Wire
+# Basics
+## Operators
+Math: `+, -, *, /`
+
+## Wire
 Wire is directional. We often use `assign lhs = rhs` drive the right signal to left. This assignment is a **continuous**(the change of right will conducted to left immediately when the voltage change), it's not a one-time assignment.
 The port(input and output) on a module also have a direction.
+When the module become complex, we will declare a wire in the module `wire wire_name;`.