From 8891517cef2e17839e5a3e528690cf00d22a245f Mon Sep 17 00:00:00 2001
From: RainBus <rainandbus@gmail.com>
Date: Thu, 30 Nov 2023 19:02:24 +0800
Subject: [PATCH] vault backup: 2023-11-30 19:02:24

---
 .obsidian/app.json       |  2 +-
 .obsidian/workspace.json | 12 +++++++-----
 Books/HDLBits/Verilog.md |  3 +++
 3 files changed, 11 insertions(+), 6 deletions(-)
 create mode 100644 Books/HDLBits/Verilog.md

diff --git a/.obsidian/app.json b/.obsidian/app.json
index 1691202..995a018 100644
--- a/.obsidian/app.json
+++ b/.obsidian/app.json
@@ -1,7 +1,7 @@
 {
   "promptDelete": false,
   "newLinkFormat": "relative",
-  "attachmentFolderPath": "./assets/Overview",
+  "attachmentFolderPath": "./assets/Verilog",
   "showUnsupportedFiles": false,
   "newFileLocation": "current",
   "useMarkdownLinks": true,
diff --git a/.obsidian/workspace.json b/.obsidian/workspace.json
index 3e9e935..02218e3 100644
--- a/.obsidian/workspace.json
+++ b/.obsidian/workspace.json
@@ -13,7 +13,7 @@
             "state": {
               "type": "markdown",
               "state": {
-                "file": "Books/编译原理/Overview.md",
+                "file": "Books/HDLBits/Verilog.md",
                 "mode": "source",
                 "source": false
               }
@@ -93,7 +93,7 @@
             "state": {
               "type": "backlink",
               "state": {
-                "file": "Books/编译原理/Overview.md",
+                "file": "Books/HDLBits/Verilog.md",
                 "collapseAll": false,
                 "extraContext": false,
                 "sortOrder": "alphabetical",
@@ -110,7 +110,7 @@
             "state": {
               "type": "outgoing-link",
               "state": {
-                "file": "Books/编译原理/Overview.md",
+                "file": "Books/HDLBits/Verilog.md",
                 "linksCollapsed": false,
                 "unlinkedCollapsed": true
               }
@@ -133,7 +133,7 @@
             "state": {
               "type": "outline",
               "state": {
-                "file": "Books/编译原理/Overview.md"
+                "file": "Books/HDLBits/Verilog.md"
               }
             }
           },
@@ -166,8 +166,10 @@
   },
   "active": "82a60b2f86acd8d6",
   "lastOpenFiles": [
-    "Study/DL/吴恩达深度学习课程/Lesson 1.md",
     "Books/编译原理/Overview.md",
+    "Books/HDLBits/Verilog.md",
+    "Books/HDLBits",
+    "Study/DL/吴恩达深度学习课程/Lesson 1.md",
     "Books/编译原理",
     "Books/未命名.md",
     "Study/DL/吴恩达深度学习课程/Other.md",
diff --git a/Books/HDLBits/Verilog.md b/Books/HDLBits/Verilog.md
new file mode 100644
index 0000000..3bd6663
--- /dev/null
+++ b/Books/HDLBits/Verilog.md
@@ -0,0 +1,3 @@
+## Basics
+### Wire
+Wire is directional.
\ No newline at end of file