Obsidian/Books/HDLBits/Verilog.md

Basics

Operators

Math: +, -, *, /

Wire

Wire is directional. We often use assign lhs = rhs drive the right signal to left. This assignment is a continuous(the change of right will conducted to left immediately when the voltage change), it's not a one-time assignment. The port(input and output) on a module also have a direction. When the module become complex, we will declare a wire in the module wire wire_name;.