Rain-Bus/Obsidian
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

vault backup: 2023-12-01 10:26:25

Browse Source
This commit is contained in:
Rain&Bus
2023-12-01 10:26:25 +08:00
parent 28a6309769
commit 2be3789033
1 changed files with 2 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
Books/HDLBits/Verilog.md
View File

@@ -1,3 +1,4 @@
## Basics ## Basics
### Wire ### Wire
Wire is directional. Wire is directional. We often use `assign lhs = rhs` drive the right signal to left. This assignment is a **continuous**(the change of right will conducted to left immediately when the voltage change), it's not a one-time assignment.
The port(input and output) on a module also have a direction.